This invention relates generally to a local interconnect metallization process for an integrated circuit. More particularly, the present invention relates to a layered local interconnect that can be fabricated in a manner that is compatible with ferroelectric capacitors and ferroelectric memory circuits.
Local interconnect has been widely used in DRAM applications to increase packing density-and reduce parasitics. In typical DRAM applications, the local interconnect is used to provide a localized conductive path between the gating transistor of a memory cell and the corresponding storage element, which can be a capacitor or the gate of an adjacent transistor used as a capacitor. A typical local interconnect for a DRAM memory cell 10 is shown in the cross-sectional diagram of FIG. 1. Memory cell 10 includes a storage element and a gating transistor located generally at 10A and 10B, respectively. Memory cell 10 is thus a one transistor, one capacitor ("1T-1C") type of cell. The storage element in FIG. 1 is an MOS transistor configured as a capacitor (a "capacitor-connected transistor"), although a separate trench capacitor or other types of integrated capacitors can be used. The capacitor-connected transistor 10A is configured so that its gate 18A serves as one electrode of a capacitor and source/drain regions 14A and 14B are coupled together and serve as the other electrode of the capacitor. The actual coupling of source/drain regions 14A and 14B and subsequent metallization thereto is not in the plane of FIG. 1 and is therefore not shown. The portion of oxide layer 20A underneath gate 18A serves as the dielectric material for the capacitor-connected transistor 10A. Gating transistor 10B includes a gate 18B, and source/drain regions 14C and 14D. The portion of oxide layer 20B underneath gate 18B serves as the gate oxide for transistor 10B. Capacitor 10A and transistor 10B are fabricated on a substrate 12, generally silicon, and are electrically isolated from each other with a field oxide layer 16B. Memory cell 10 is isolated from other such cells in an integrated memory array through field oxide layers 16A and 16C.
In a typical DRAM local interconnect process, the local interconnect is fabricated using a second level of polysilicon or polycide such as tungsten silicide (WSi) or titanium silicide (TiSi.sub.2). The first level of polysilicon is typically used for transistor gates 18A and 18B. As shown in FIG. 1, this second level of polysilicon 22 electrically ties source/drain region 14C of transistor 10B to gate 18A, which is the top electrode of capacitor 10A. Local interconnect 22, therefore, completes the; electrical connection between the two components of memory cell 10. The exact configuration of local interconnect 22 is often altered from that shown in FIG. 1 depending on the storage and access requirements of the DRAM user and the metal interconnect layout fabricated later in the process. In FIG. 1, another oxide layer 24A is formed on the surface of local interconnect 22 (with oxide layer 24B forming on oxide layer remnant 20C). Oxide layers 20 and 24 are etched to expose source/drain region 14D. A metal interconnect 26 is formed to contact source/drain region 14D.
An equivalent electrical schematic of DRAM memory cell 10 is shown in FIG. 2. Memory cell 10 includes a gating transistor 10B and a capacitor 10A. The top electrode of capacitor 10A is designated 18A to correspond to gate 18A shown in FIG. 1. Similarly, the bottom electrode of capacitor 10A is designated 14A, 14B to correspond to source/drain regions 14A and 14B shown in FIG. 1. The bottom electrode node of capacitor 10A is also designated "VCC/2", which is the reference voltage normally applied to this node in most DRAM applications. The gate of transistor 10B is designated 18B to correspond to the gate, shown in FIG. 1, and is also designated "WL", corresponding to the word line connection used in a typical DRAM cell. The "top" source/drain region of transistor 10B is designated 14D, 26, which corresponds to source/drain region 14D and metal interconnect layer 26 shown in FIG. 1. This node is also designated "BL", corresponding to the bit line connection used in a typical DRAM cell. The "bottom" source/drain region of transistor 10B is designated 14C, which corresponds to source/drain region 14C shown in FIG. 1. Finally, the desired local interconnect 22 is shown as a dotted line, which electrically connects capacitor 10A to transistor 10B to complete the cell.
In many DRAM approaches, the transistors and storage elements are fabricated simultaneously (i.e. the storage element is typically the gate region of a transistor) with the same dielectric material, silicon dioxide (SiO.sub.2). However, in the fabrication of a ferroelectric memory, the transistor gates and storage elements typically include different dielectric materials. Silicon dioxide is used to form the transistor gates, whereas the storage element includes a ferroelectric dielectric material such as lead zirconate titanate (PZT). Because different materials are used, the ferroelectric storage elements (ferroelectric capacitors) are fabricated at a later process step and are typically fabricated close to or on top of the earlier fabricated memory cell transistor.
The typical DRAM local interconnect may not be useable in a ferroelectric memory cell because of these differences in the process flow. For example, polysilicon cannot be used to contact PZT directly because it will substantially impair the switching characteristics of this material. It is essential, therefore, that a local interconnect for a ferroelectric memory cell be compatible with the ferroelectric material used and also be compatible with conventional integrated circuit fabrication techniques.
What is desired is there, fore, is a method of forming a local interconnect that is compatible with an integrated circuit ferroelectric memory cell.